QuickEmbeddedTips

The Swedish company Strategic Test has announced a SODIMM-sized processor module using Freescale's recently announced i.MX25 SoC (system-on-chip). The Linux-compatible "Tx-Star" features a 400MHz i.MX257, 64MB of RAM, 128MB of flash, and an LCD controller, and is available with an evaluation baseboard.

Lvalue or location value is an address that is stored into while rvalue is the "read" value, ie., value of a constant or the value stored at a location. In the assignment

a = 31;

we have the lvalue of a used on the left hand side and the integer contant value 31 assigned to this location.

In the assignment

fromELF is the ARM image conversion utility.
supports plain binary, Motorola 32-bit S-record format, Intel Hex-32 format,Byte Oriented Hex format.

To convert an ELF file to a plain binary (.bin) file, enter:
fromelf --bin -o outfile.bin infile.axf

To produce a plain-text output file that contains the disassembled version of an ELF file

armcc [PCS-options] [source-language] [search-paths] [PCH-options]
[preprocessor-options] [syntax-checking] [C++-language] [output-format]
[target-options] [debug-options] [code-generation-options]
[default-object-extension] [diagnostic-options] [warning-options]
[additional-checks] [error-options] [source]

[PCS-options]

How to Write ROM library for ARM Processor?

Semaphores, another important contribution by E. W. Dijkstra,
can be viewed as an extension to mutex locks. A semaphore is an object
with two methods Wait and Signal, a private integer counter and a
private queue (of threads). The semantics of a semaphore is very simple.
Suppose S is a semaphore whose private counter has been

Low cost flash microcontroller with a built-in 10-base-T ethernet MAC+PHY, and reasonable program memory(32-64k)

Microchip ENC28J

CodeSourcery give you free toolchain but you have to pay for debugger and Eclipse IDE support. FSF is free (as in freedom !)

1) GNUARM toolchain.
http://www.gnuarm.com/

2) Rowley provides a professional quality IDE,Debugger for arm GCC toolchain at a very

reasonable price.

Some general tips for reducing the Code size for firmware.

1) Use the Map file.
Configure the tool to generate a MAP file. Most linker/locators will generate a fairly detailed map file, which you can use to hunt down the biggest targets for code reduction.


2) Use compiler optimization.

why should we do memory remapping in ARM7 ?

Most ARM cores support two vector locations 0x0 or 0xFFFF0000, controlled via a signal sampled at reset and a bit in CP15. Lets say that the core is configured to have its vectors at 0x0, then as the core comes out of reset it will start fetching instructions from 0x0. There has to some valid code at this position. So generally you would require to have a nonvolatile memory at this location.

These tips can be used while designing any embedded Real Time application

Process Tips
1) Follow the Coding convention religiously. These include variable,Data structure, Functions names etc. It makes the code easy to maintain.
2) Have Code review and discussion with fellow programmers.
3) Prepare the documentation before implementations.

Design Tips
1) The detailed design should cover all the functionalities with a separate diagram for each. The diagram should display the Process-Flow, data flow, dependency graphs, data relationship. Any State machines should be explained separately.
2) The design should mention the worst case timings for servicing functionalities. The system behaviour can then be confirmed to this while testing.
3) Perform memory analysis to compute the memory usage. While testing this should be confirmed
4) Possible unhandled error cases should be mentioned separately with the reason for their exclusion.

Coding
1) Avoid using global variables. If needed encapsulate all of them into a single data structure.
Now Control the access of this data structure to prevent race-conditions.
2) Avoid fine grain optimization during the first implementation. Keep it simple.
3) Use timers for delay than empty loops. You ca poll the count down value of a timer instead.
4) Use StateMachine, Lookuptables than using many if-else statements.

Testing Tips
1) Measure the execution timings of critical portions of code.
2) Measure and record the interrupt latency for the system.

How do RTOS kernel keep track of time ?

Every kernel provides a mechanism to keep track of time. This is done by a hardware timer which interrupts the CPU periodically.
The ISR for this timer invokes a service provided by the kernel, which is responsible to update time dependent variables. This ISR is generally called a Clock Tick ISR. Kernel maintains a special list to keep track of tasks that are waiting for the time to expire. This is called delayed task list.

Q: What is interrupt nesting?

Pre-Emption of low priority Interrupt by another high priority interrupt is known as Interrupt nesting.
If a high priority interrupt pre-empts the lower priority interrupt, then the higher priority Interrupt context would be saved on the previous lower priority one. We now say the depth is two and nesting is two.

Q: How is nesting of interrupt handled ?

Most architectures have two stacks. Task and Interrupt stack. The size of interrupt stack is decided by the maximum depth of nesting. If an ISR gets interrupted, the interrupt stack saves the context of the first interrupt service routine. The context here is generally all the registers, PC and local variables. When the second ISR executes its return from interrupt instruction, it pops back to the first ISR, stack,registers and interrupt level. Now when this first ISR routine executes return from interrupt, then it may back to the task level, the stack is restored to the task stack and the registers and processor level go back to the normal task level.

Q: How to avoid nesting of interrupts?

Nesting of interrupts can be avoided by disabling the interrupt as soon as interrupt service routine is invoked.
In most architecture, interrupts are automatically disabled on invoking ISR.

Q:For a level triggered interrupt, if the interrupts are not disabled, will it result in repeated invoking of ISR?

Yes. If an interrupt is level triggered, then you need to reset the level
when the interrupt is serviced. IF you fail to reset the interrupt
request, the interrupt will recur when interrupts (at that level) are
re-enabled. Usually that would be when the ISR returns.

Which -mcpu option must be used to gcc-compile for an arm processor ?

-mcpu specifies the name of the target ARM processor. GCC uses this name to determine what kind of instructions it can emit when generating assembly code.
These are the -mcpu options used for ARM processors with gcc.